A Review of STT-RAM, SRAM, and eDRAM and Methods of Optimization for Computer Architecture

The following Capstone Report seeks to outline difference in cache designs but more thoroughly into the computer architecture of STT-RAM, SRAM, eDRAM. It begins by outlining the use of cache followed by the different protocols for implementation including: direct mapping, fully associative, and set associative configurations. An area of interest in this study is implementing STT-RAM over SRAM by partitioning the second cache level in two. The method to which this was done and specialized resulted in an increase performance in the PARSEC benchmark. eDRAM cache designs were also improved by using dead-line prediction in one case demonstrating an improved energy efficiency. Overall each cache configuration selected by the research groups showed an increase in performance and energy efficiency in most cases. Keywords—STT-RAM, eDRAM, SRAM, Cache Latency NonVolatile Memory, Retention-Relax Design, Process Variation Aware Non-Uniform Cache Access, Direct Mapping, Fully Associative Mapping, And Set Associative Mapping